Publication date: 06 July 2010
More than 40 years after first being introduced, and despite competition from programmable and system-on-chip devices, demand remains for 74-series logic devices. These often provide an efficient and cost-effective solution to challenges such as interfacing to displays, driving signals across boards or backplanes, and performing numerous bit-manipulation, signal masking, chip-enable and similar functions.
Successive new logic families have emerged, which are also characterised by lower operating voltages to interface with other low-voltage devices such as FPGAs, memories and microcontrollers built at today’s leading-edge 65nm and 45nm nodes. These can operate at core voltages as low as 1.2V, while I/O voltages may typically be 3.3V, 2.5V or 1.8V.
To build complete systems taking advantage of the full variety and performance of components available, designers need access to logic families operating at a variety of voltages; it is usually not feasible to build an entire system using devices operating from the same supply-voltage level. Moreover, successful system design is dependent on effective methods to interface between devices operating at dissimilar voltage levels.
This has several caveats for logic design, since devices must be able to determine the correct nature – true or false – of the signal presented at any input. This is necessary to ensure interoperability between different types and generations of devices, and calls for components to translate between various levels, such as 3.3V to 5V and vice versa, or between these and any of the lower voltage standards now in use.
Figure 1 shows the threshold levels for different supply voltages and device technologies. To interface two devices successfully, certain requirements must be met:• The VOH of the driver must be greater than the VIH of the receiver• The VOL of the driver must be less than the VIL of the receiver• The output voltage from the driver must not exceed the I/O voltage tolerance of the receiver
These conditions imply that a device with higher I/O voltage can drive a lower-voltage device without problems, provided the input of the lower-voltage device is able to withstand the maximum voltage applied.
Over-voltage tolerant devices are built with no clamp diode to VCC at the input, and with a thicker gate-oxide layer enabling the device to tolerate voltage levels higher than the device’s own VCC. There are some performance limitations, however. If the input signal has slow rise and fall times, the fact that the device switches at the thresholds of the lower-voltage standard will tend to distort the output signal. This may produce a slight change in the duty cycle of a clock, for example.
On the other hand, a lower-voltage output is typically not able to drive a higher-voltage input. Devices with open-drain outputs are able to drive inputs at higher or lower voltage levels, with the use of an external pull-up resistor. Figure 2 illustrates how the push-pull circuit drives an additional open-drain driver, and the source of the output transistor is connected to the VCC of the driven device via a pull-up resistor. This architecture is suitable for low-to-high or high-to-low translation.
The 74LVC06A/74LCX06 is an example of a low-voltage (3.3V) hex inverter/buffer featuring overvoltage-tolerant inputs and open-drain outputs. This device is able to drive data lines when either a high-to-low or low-to-high voltage translation is required.
One drawback of level shifting using an open-drain device is that when the output transistor is turned on, during an output-low condition, a constant current will flow through the pull-up resistor to ground. This results in relatively high power consumption. Increasing the value of the pull-up can reduce this current, but at the expense of a longer time constant due to the combined effect of the pull-up resistance and the load capacitance; this tends to slow down signal edges, which can be impractical in some high-speed switching or bus applications.
A translating bus switch, or FET switch, is another class of device capable of interfacing between two dissimilar logic voltage domains. The schematic of figure 3 shows how an Enable signal is used to turn the bus switch ON. This connects the A port to the B port, and provides voltage translation that tracks VCC. The 74CBTD and CB3T logic families contain bus switches in a number of widths such as dual or quad configurations. The CB3T family fully supports mixed-mode signal operation for interfacing between 5V and 3.3V or between 5V/3.3V and 2.5V environments, and works with VCC from 2.3V to 3.6V. The CBTD family allows level shifting between 5V and 3V.
When translating a byte- or word-wide bus, Read or Write signals can be used to enable the switch. When performing voltage translation with smaller 1-wire or 2-wire buses, a translator such as the Maxim MAX3370–MAX3393 family implements internal circuitry enabling the devices to operate across all translation levels, support mixed low-to-high and high-to-low logic transitions, and perform unidirectional and/or bidirectional translation. Figure 4 shows the MAX3373, which eliminates the need for a separate Enable pin and also integrates a speed-up switch to minimise the effect of capacitive loading on signal speed. This can allow data rates as high as 20Mbps for signals produced by a push-pull driver.
There are, however, some drawbacks to voltage-level translation using a bus switch. In the diagram of figure 5, a Texas Instruments SN74CB3T3306 comprising two 1-bit bus switches is operated at VCC 3V and used to interface a 3V bus with a 5V (TTL) bus.
When interfacing from the 3V bus to the 5V bus, the VOH signal on the 5V side is clamped to about 2.8V. Although this is a valid VIH level for a 5V TTL device, it has a relatively low noise margin of 2.8V – 2.0V = 800mV. In addition, because the high output from the CB3T device is not driven all the way to the VCC rail, the 5V receiver has high power consumption.
In addition, if a CB3T device is used to interface a 3V CMOS bus to 5V CMOS logic a pull-up resistor would be required since 2.8V is not an adequate VIH voltage for 5V CMOS logic.
Dual-supply devices are able to overcome some of the challenges to do with speed and power consumption when interfacing logic domains of various voltages. These devices use two supply voltages to interface the A side operating at VCCA with the B side operating at VCCB. A DIR input is also provided enabling bidirectional level translation from A to B or B to A. Dual-supply devices are available in a variety of bit widths and cover nearly every supply-voltage node in use today.
Another advantage of dual-supply devices is their active current drive, which allows them to overcome the CR loading that can slow signal edges in circuits using pull-up resistors. They can also be used with long trace lengths, if required. Various configurations are available, including multi-bank devices such as the 74AVCB320245. This implements four banks of eight bits each, allowing one bank to be used, for example, to translate from 3.3V to 1.8V while another bank is setup to translate from 1.8V to 3.3V. 74AVC-family devices are available from major manufacturers including Texas Instruments (TI), NXP, Fairchild and STMicroelectronics (ST).
As logic technologies advance, moving toward ever-lower operating voltages, new bus translation devices using technologies such as TI AUC or similar technologies also emerge to translate up or down for logic in the range 1.1V to 3.3V. In addition, non-74 series level translators such as the Fairchild FXL family or ST’s STxG devices take advantage of dual-supply flexibility to interface to a variety of peripherals including memory cards, I2C ports or UARTs. The FXL series is capable of translating up or down between 1.0V and 3.3V. ST’s level translators are built for a variety of voltage ranges between 1.4V and a maximum of 5.5V, and span interface widths from 1-bit (ST1G) to 16-bit (ST16G).
Typical features of these emerging families include extensive use of power saving technologies, as well as ultra-small packaging such as QFN leadless styles or µTFBGA to serve portable and battery-powered products such as mobile phones, cameras, personal media players and PDAs.
The next step in voltage-level translation is to make the translation direction independent from the processor software control. TI, with its TXB01xxx and TXS01xxx families, has achieved this with a more sophisticated architecture based on CMOS logic inverter and buffered push-pull for the buffered type of translators, or with a combination of integrated pull-up resistors and pass transistor for auto-direction-sensing switch-type translators. At different interface voltage levels TI’s auto-direction-sensing translation devices are ideal for point-to-point topologies. They improve connectivity between next-generation processors and peripheral devices by eliminating the requirement for direction-control signals used by traditional voltage-level translation devices. This decreases the control software complexity while saving valuable GPIO signals on core processors. These parts feature automatic reconfigurable I/O buffers, so that each I/O port is configured as both an input and an output.
Successive generations of CMOS fabrication processes operate from progressively lower supply voltage levels. Designers need to be able to use these low-voltage devices to take advantage of the latest high-speed, low-power silicon, but must also be able to connect to other subsystem components such as LCDs. These tend to require transceivers operating at higher voltages. This brings a demand for voltage-level shifting functions.
A number of logic families now available enable designers to interface from today’s lowest operating voltages, as low as 0.8V for logic and 1.2V for other devices such as microcontrollers, FPGAs, ASICs and ASSPs, to circuitry operating at higher CMOS voltages up to 3.3V or 5V. Selection, as always, demands a trade-off between power consumption, speed, size, and cost.
