Publication date: 18 May 2010
The use of low inductance decoupling capacitors is an attractive design option, as opposed to the use to standard ceramic capacitors. The implementation of low inductance capacitors saves board space, reduces board weight and improves overall system reliability.
Low inductance capacitor designs first emerged with on package decoupling and quickly found its place in PCB decoupling of satellite and spacecraft processor cards. Currently low inductance capacitors are being used in a variety of high data speed critical circuits such ad video links and image processing.
Over the past 10 to 12 years, decoupling capacitors have evolved from multilayer ceramic capacitors (MLCCs) to reverse geometry low inductance chip capacitors (LICCs) to multi-terminal inter-digital capacitors (IDCs) to low inductance capacitor arrays (LICAs), and most recently, to bottom-terminated land grid arrays (LGAs) (Figure 1).
This evolution has been driven by the requirements of lower inductance power delivery systems to keep pace with switching speeds and transistor density in silicon processors. Low inductance capacitors reduce noise to such an extent that a lesser number of capacitors need to be used. The reduction in the number of capacitors needed for decoupling thereby saves board space and weight while the reduced components and solder connections improves system reliability.
Capacitor inductance is a result of the interaction of magnetic flux fields created by the electric current flow in and out of the device on a circuit board. The current path or “loop” includes not only the multilayer capacitor’s internal electrodes and external termination, but also the power planes, vias, mounting pads and solder fillets of the substrate / package (Figure 2).
Figure 2. ESL in a mounted MLCC directly relates to the area of an idealized current loop (LH x LW) formed in the board and capacitor.
In a simple analysis, there are two basic strategies to reduce the equivalent series inductance (ESL) of a capacitor. • First, make the area of the current loop formed by the mounted device as small as possible• Second, employ multiple, parallel loops to reduce the net inductance.
These strategies are somewhat related as one considers that the current can be considered to flow through an idealized conductor loop with a given height and width, defining a loop area, and in the third dimension, this loop has a given span, that is perpendicular to the direction of current flow. To minimize ESL, loop area is minimized, and loop span is maximized. This is the strategy that led to the development of the reverse geometry, LICC, which when compared to an equal case size MLCC, has an effective current loop with smaller “area” and greater span to give the LICC an inductance reduction of ~ three to four times (Figure 3).
Figure 3. Reverse geometry LICC’s have lower ESL than MLCC’s because of smaller current loop area and greater span length.
As shown in Figure 4, the long-side terminations of LICC’s can be segmented with terminals of alternating polarity, forming several parallel, small-area current loops in the IDC device. The lumped inductance of an 8-terminal IDC is approximately 3 times lower than a LICC of equal case size. In IDC’s, inductance can be further reduced by increasing the number of parallel terminal contacts on any of the four sides of the device, preferably with decreased pitch.
Figure 4. Internal electrode schematics show how IDC terminals are segmented in alternating polarity to get small parallel current loops and thus lower ESL than LICC’s.
This is an extension of the strategy of more parallel loops with smaller current loop area. Finally, for a given style of capacitor with a set number of terminals, whether MLCC, LICC or IDC, the inductance can be reduced by choosing a smaller case size part; in other words, the case size is directly related to the current loop area.
Therefore, consequences of the evolution of low inductance decoupling capacitors from MLCC to IDC, with smaller case sizes, are an increase of the complexity of the terminal configuration and a related, but unwanted, generalized reduction of the maximum available capacitance per device. The challenges in both capacitor fabrication processes and in board assembly operations, brought on by this evolution, give an opportunity for improvement.
All of the capacitors discussed above share some common features: • The internal electrodes are oriented horizontally, that is, parallel to the substrate after mounting• The electrical signals enter/exit the device through terminals located on the side of the capacitor.
A new capacitor design changes the configuration of the internal electrodes to have vertical orientation and permits the I/O terminals to be located on the bottom of the capacitor, so signals feed directly into the circuit board (Figure 5).
Figure 5. LGA capacitors have patterned vertical electrodes coupled with precision termination to form very small current loops and very low ESL.
To emphasize the bottom, rather than side, connectivity, this style of device is called a land-grid array capacitor. The LGA capacitor exploits the same strategies listed above for obtaining low inductance, but the internal electrode configuration allows loop areas to be greatly reduced relative to the other designs. Because of the efficiency of the current cancellation within the capacitor that is achieved by the new electrode / terminal structure, a relatively simple 2-terminal LGA can have equivalent inductance to multi-terminal IDC (Figure 6).
Low inductance land grid array capacitors provide simple PCB layout and implementation while offering optimized low inductance performance.
Figure 6. 1µF 0306 2T-LGA’s have simplified LICC-like terminals
The low inductance capacitor array remains the leading choice in decoupling high performance semiconductor packages. LICAs utilize a C4 solder ball termination with either Sn/Pb or Pb free solder balls available. Vertical electrodes as well as minimized board loop area insure LICA performance in virtually all decoupling applications.
Low inductance capacitors have evolved primarily due to new termination processes now becoming implemented in capacitor manufacture. These new termination processes allow the capacitor terminals to be focused on current cancellation loop areas and spans in the decoupling capacitor. Board layout must be optimized (low inductance layout rules) to allow for the low inductance capacitor properties to remain after board attachment.
Low inductance capacitors are used in an ever-expanding number of high-speed applications. Their ability to lower ground plane impedance has the potential to reduce radiated emissions. Additionally, low inductance capacitors can help reduce component count, system weight and layout complexity all while improving system reliability.
