Publication date: 25 September 2007
According to research by Instat, in 2006 there were 75 million DBS receivers for digital TV. While the market is considered to be mature in North America, the launch of the first DBS satellite in China and the start of commercial digital satellite TV services in India will foster explosive growth as DBS provides a cost-effective transmission medium for TV broadcasters in developing countries.
A DBS system has two major sub-blocks for signal processing, a low noise block (LNB) down-converter and a DBS TV receiver. The LNB down-converter is located inside the satellite dish antenna housing and translates the satellite spectrum from the C, Ku or Ka band down to the L band (0.9 to 2.2 GHz). The DBS TV receiver is located inside a set-top box (STB). It performs the final down-conversion to baseband, as well as signal processing functions such as demodulation, MPEG decoding, display processing and analog audio/video encoding (NTSC/PAL).
The DBS receiver’s four functional blocks are an RF tuner, a QPSK demodulator/channel decoder, a host processor and an LNB supply controller. The RF tuner down-converts the signal from L-band to baseband; the QPSK demodulator/channel decoder recovers the bitstream. The host processor decodes the MPEG data stream and generates video and audio output signals to the TV. The LNB supply controller generates a 13/18V dc signal on the RF coax to power the rooftop LNB module. The receiver also superimposes an ac control signal on this dc power feed to select the desired LNB polarization.
Over the past decade the RF tuner in DBS receivers has moved from a high-IF dual-conversion architecture to a direct-conversion zero-IF (ZIF) topology. More recently the market introduced a monolithic CMOS low-IF receiver. There are important differences between the various RF tuner architectures in DBS receivers, which impact the designer and the end system.
The first silicon satellite TV tuners on the market used a high-IF dual-conversion architecture (shown in Figure 1), which can achieve good image rejection performance. A high-IF dual-conversion architecture uses an external IF SAW as an inter-stage filter to limit image rejection requirements inside the tuner IC. However, these super-heterodyne tuners require an overly complex, two stage mixing process. First, the tuner converts the signal from L-band to a high intermediate frequency (IF) (e.g. 480 MHz). In a second mixing stage it converts the signal to baseband. High-IF dual architectures also suffer from greater power dissipation due to the required external circuitry operating at a high IF frequency and a larger bill-of-materials from these additional external components.
Advancements in IC processing and design now enable a direct-conversion DBS tuner, in which the RF signal is down-converted in a single mix from L-band directly to baseband (shown in Figure 2). Since the image frequency is the desired signal itself, the direct-conversion receiver does not suffer from image rejection issues. The tuner architecture is simplified by eliminating the off-chip SAW filter, the second IF mixer and the high-IF gain stages to decrease die area, lower power dissipation and reduce external component count and total system cost.
There are some drawbacks to direct conversion. There are three key sources contributing to a potential DC offset between I and Q channels: device mismatch, local oscillator (LO) leakage to the RF input and RF leakage to the LO input of the mixer. dc offset may cause saturation of the signal path amplification stages and should be avoided. In time domain duplexing (TDD) communication systems, such as GSM, the dc offset can be measured and canceled while the communication channel is off. However digital satellite TV transmission is continuous. Therefore any dc offset can only be mitigated by a dc offset servo loop with a narrow loop bandwidth. The narrow bandwidth ensures that signal degradation due to the offset cancellation loop remains small, and it can be fully recovered by the demodulator’s forward error correction (FEC) circuit. But such a servo loop with narrow bandwidth requires very large ac coupling capacitors, which usually cannot be integrated on-chip.
A second drawback of direct-conversion tuners is that 1/f noise of the devices in the signal path may significantly degrade the tuner noise figure, since the 1/f noise overlaps with the desired (complex) signal frequency spectrum positioned at zero-IF (ZIF). Most existing ZIF DBS tuners are implemented in a bipolar technology to take advantage of the fact that bipolar transistors have a much lower 1/f noise when compared to MOS transistors. Several attempts to implement direct-conversion DBS tuners in CMOS processes have used passive mixers that do not cause a large 1/f noise hit since there are no active transistors in the signal path. However, a passive mixer has a conversion loss, causing the noise of the baseband circuitry to negatively affect overall receiver noise performance.
Following the tuner, the demodulator is a digital-intensive IC with an A/D converter front end digitizing I and Q ZIF signals. A CMOS implementation of the demodulator decreases die area and power dissipation. The third functional block of the receiver, the MPEG host processor, is a large SoC which is naturally implemented in an advanced CMOS process (130, 90 and moving to 65 nm CMOS).
The cost of a standalone bipolar tuner is very competitive when using mature bipolar processes with a 0.6 to 0.2 μm lithography and it provides devices with high transition frequencies (fT=25 to 50 GHz) to allow multi-GHz tuner implementation. However, while developing a single-chip tuner-demodulator in an advanced BiCMOS process is possible, it has a cost penalty since the expensive multi-mask process needs to be applied to a large area consisting of predominantly digital CMOS circuitry.
A more viable integration path is offered by a system-in-package (SiP) approach in which components including a bipolar tuner, CMOS demodulator and MPEG processor are available in a single package. The major advantage of SiP is a faster time-to-market, since the existing tuner and demodulator die can be re-used. The main drawbacks of SiP integration are the higher packaging costs, complicated power dissipation and bondwire parasitic coupling issues.
Alternative system partitioning is to have a standalone RF tuner IC in a bipolar or BiCMOS process, and integrate the demodulator and MPEG processor into a single CMOS IC. This is known as the ‘demod-on-host’ approach (see Figure 3). However, from a systems viewpoint, this is an artificial partitioning. The “source decoder” IC now becomes transmission-medium dependent, so a different host IC is needed for cable, terrestrial and satellite receivers. This impacts economies of scale and causes the OEM more qualification and assembly costs by prohibiting the development of a “common hardware platform” (see Figure 4). A common platform that only has a transmission medium-specific RF front-end and interfaces to a host processor that is independent from the DTV delivery method (satellite, cable, terrestrial, IP). Clearly the common platform is a more logical and cost-effective approach to system partitioning.
A ZIF receiver is shown in Figure 2. While a fixed-gain amplifier may have a better noise figure and linearity, the RF low-noise amplifier (LNA) is typically implemented as a cascade of a highly linear fixed-gain amplifier followed by a continuous variable gain attenuator (VGA). The amplified L-band RF signal is input to an analog quadrature mixer which converts immediately to baseband. A baseband VGA, followed by a low-pass anti-aliasing filter, provides I and Q quadrature analog outputs to the demodulator chip. Off-chip coupling capacitors are needed due to the very low corner frequency required to mitigate any dc offset. If a large gain step is applied to the signal path (as in the case of a discrete-step AGC), the settling time will increase to several milliseconds, resulting in a large burst of erroneous data which cannot be recovered by the FEC. Therefore, direct conversion tuners need to use a continuous AGC loop using transistors operating in the active region. These contribute noise and degrade the linearity of the signal path when compared to an AGC with only passive elements such as resistors and switches.
An advantage of a ZIF tuner is that the bandwidth of the desired channel at the ADC input is at its minimum. In a DBS system, the 3 dB signal bandwidth is approximately 1.35 times the symbol rate, which can vary from 1 to 45 MBaud. Therefore, at ZIF, the maximum frequency on both the I and Q channels is about 30 MHz, which requires between 80 and 90 MSPS ADC sampling speeds. There is also only one channel present at the ADC input, as adjacent channels are strongly attenuated by the variable bandwidth low-pass filters inside the tuner. The result is a lower required dynamic range and a low ADC resolution (typically 6 bits). Both the lower resolution and sampling frequency lead to decreased power dissipation in the ADCs.
Multiple LC oscillators are used to generate an RF synthesizer with sufficiently low phase noise. The minimum channel separation can be as low as ~1 MHz. Since an integer-N PLL requires a bandwidth at least ten times lower than the reference frequency, a very low bandwidth PLL is needed. This type of PLL increases channel zapping time and slows channel scanning. To achieve faster PLL settling time while preserving fine frequency tuning resolution for adjacent channels, direct-conversion DBS tuners often use fractional-N PLLs. A fractional-N synthesizer typically has higher power dissipation and is more complex, requiring careful analysis of the fractional spurs and system stability due to the presence of a high-order delta-sigma modulator loop.
The relatively low PLL bandwidth requires an off-chip loop filter, which brings the sensitive oscillator control node to a signal trace on the PCB. In stand alone tuners, the noise coupling to the VCO control node can be contained with judicious board design. At the board level, the main spur coupling sources are the switched-mode power supply regulator, the reference tones radiated by the crystal oscillator and other tones generated by the digital ICs.
In the case of a multi-die SiP assembly, careful analysis and design of all die bondings has to be performed to minimize magnetic coupling between the digital demodulator, LNA input bondwire, frequency synthesizer reference clock crystal bondwire, off-chip PLL loop filter bondwire and on-chip inductors of the LC oscillators. Since the RF signal in a ZIF tuner is converted directly to baseband, it is not possible to perform any frequency management to avoid certain spurious tones.
Late 2005, Silicon Labs pioneered a low-IF DBS tuner/demodulator architecture which circumvents the impact of 1/f noise on the tuner noise figure and eliminates the signal path dc offset. By choosing an IF larger than the 1/f noise corner frequency, “flicker noise” is largely prevented on the signal path. In addition, the tuner output signal is no longer residing at dc. Since the chosen IF is around 40 MHz, the coupling capacitors can be reduced to pF sizes, enabling any dc offset to be removed from the signal path using on-chip capacitors.
In a digital low-IF tuner implementation, an analog mixer converts a cluster of L-band RF channels to the low-IF frequency. The signal is filtered and A/D converted. The final down-conversion to baseband is performed in the digital domain, resulting in a higher quality filtering and lower area compared to an analog channel filter implementation on the tuner side. The result is a digital low-IF tuner that is the ideal candidate for a CMOS implementation. The tuner also enables integration with the demodulator onto a single silicon die.
Figure 5 presents the block diagram of Silicon Labs’ Si2110 low-IF DBS satellite TV receiver. Final channel selection is performed in the digital domain after the second digital mixer down-converts the signal to baseband using a numerically-controlled oscillator (NCO). The QPSK baseband signal is demodulated, and the resulting MPEG transport stream is available at the chip output. This is a truly monolithic implementation of an L-band RF-to-MPEG bitstream receiver, able to receive satellite services per the global DVB-S and the proprietary DirecTVTM DSS DBS standards.
Since a ‘low-IF’ tuner can have a higher corner frequency in the dc-offset cancellation loop vs. ZIF, the settling time after an AGC gain change is faster. This enables the use of a discrete-step AGC. Unlike a continuous AGC, a discrete-step AGC can be implemented with only resistors and switches. Compared to active transistor based attenuators, such passive AGC’s are more linear and have a lower noise impact. The higher linearity benefits the IIP3 performance of the receiver (IIP3 = +25 dBm at maximum gain on Si2110 versus a typical +9 dBm for a ZIF DBS tuner).
The first analog mixer can be driven by a simple integer-N frequency synthesizer using a coarse frequency step (e.g., 20 MHz), which can be implemented by a ring oscillator rather than an LC-based oscillator. While a ring oscillator is known to have larger phase noise, the large reference clock frequency of 20 MHz allows the use of a wide bandwidth PLL (BW = 1 MHz) which suppresses phase noise over its wide loop bandwidth. In addition, the high PLL bandwidth allows on-chip integration of the loop filter, eliminating noise and spur coupling to the sensitive VCO control line.
After the conversion to a low-IF frequency, the signal is amplified by a VGA. Together with the RF front-end attenuator, the VGA achieves the wide (90 dB) gain range required for the satellite TV application. The signal is low-pass filtered (anti-aliasing filter) and A/D converted. Since the signal is centered around 40 MHz and has a maximum channel bandwidth of about 60 MHz, the ADC sampling frequency is increased to about 200 MSPS, which is higher than for a ZIF tuner. Consequently, the initial stages of the digital demodulator also need to operate at a higher clock frequency. The wider bandwidth of the IF signal path and higher clock frequency in the ADC and demodulator core result in a larger power dissipation of the low-IF versus ZIF tuner. However, power is not the most critical parameter in STB applications; rather low-noise and spurious performance of the tuner are key features to ensure maximum receiver sensitivity for weak RF satellite input signals.
The digital demodulator requires a second PLL to provide the digital clock. Careful frequency planning is required to avoid pulling and spur injection between the two on-chip PLLs. The first is a ring oscillator, which doesn’t require any inductors and eliminates RF coupling between the digital core and the RF synthesizer. On-chip integration of the loop filter minimizes any spur coupling to the VCO sensitive control node. In a low-IF tuner architecture there is only a single major RF coupling effect, which occurs between the digital core and the LNA input bondwire. The impact of this coupling can be avoided by judicious frequency planning (i.e., slightly varying the position of the center IF prior to A/D conversion with appropriate compensation of any frequency shift in the digital demodulator).
Since all tuner and demodulator blocks can be readily implemented in CMOS, a single-chip tuner-demodulator IC can be realized. The IP is then ready for the next level of integration with the MPEG host processor.
The ZIF tuner has a degraded implementation loss (IL) at low symbol rates due to the impact of the low corner frequency dc offset cancellation loop. At high symbol rates, the IL improves. Conversely, the high-IF tuner has a degraded IL at higher symbol rates since the finite bandwidth of the off-chip SAW filter causes group delay distortions. At lower data rates the excess phase noise also causes the IL of a high-IF architecture to deteriorate. In contrast, the IL of a low-IF tuner is low and has a constant value over the entire symbol rate range since there is not a dc offset cancellation loop nor off-chip SAW filter.
A direct-conversion architecture is advantageous in communication systems with high blocking requirements (large image rejection) because the image channel is the received channel. However, in satellite TV receivers all received channels have a relatively similar power profile, relaxing the image rejection specification to between 40 and 45 dB. Therefore, the ZIF tuner has no real advantage over the low-IF tuner in DBS applications. Furthermore, the large number of parasitic coupling effects between the direct-conversion tuner and a digital demodulator makes single-chip tuner-demodulator integration difficult.
In contrast, the digital low-IF architecture offers adequate image rejection after digital I/Q calibration, while providing an inductor-less RF synthesizer implementation. An inductor-less RF LO has the additional benefit of minimizing parasitic coupling, even when the large digital demodulator is present on the same die. A ring oscillator offers a much smaller die area, which benefits both cost and parasitic substrate coupling. In addition, it also offers better spur performance and is more robust against RF pulling and pushing. In practice, a dual conversion digital low-IF tuner does not add any further complexity to the receiver, since even the ZIF tuner needs a second digital mixing stage in the demodulator to compensate for any LNB oscillator frequency drift. The primary difference between the two architectures is a wider tuning range of the NCO in the low-IF case, because its range needs to accommodate both LNB frequency drift and the slightly varying center IF of the channel cluster down-converted by the RF mixer.
A slight disadvantage of the low-IF architecture is the need for higher bandwidth IF stages and higher clock frequency digital demodulator and front-end ADCs. While this may lead to higher power consumption, the issue is mitigated as CMOS is scaled towards deeper sub-micron processes (90 nm and 65 nm) which allow for the implementation of faster digital circuits and wider bandwidth analog amplifiers within a given power budget.
Table 1 summarizes a performance comparison between the zero-IF and low-IF DBS receiver architectures.
Architecture
Direct-Conversion (Zero-IF)
Dual-Conversion (Low-IF)
LNA
Attenuator after LNA Þ lower linearity
Attenuator before LNA Þ higher linearity
AGC loop
Continuous AGC loop Þ degrades both front-end noise and linearity
Discrete-step AGC loop Þ higher RF front-end linearity and lower noise figure
Mixer/LNA
Stringent IIP2 requirement
No image rejection issue
Stringent IIP3 requirement
Need image rejection calibration
Synthesizer
Low bandwidth Þ large C Þ off-chip loop filter
Multi-LC VCO design Þ large area & noise/spur coupling
LO leakage to the LNA Þ DC-offset issue
LC-VCO Þ easy to achieve phase noise specifications
Large bandwidth Þ low C Þ on-chip loop filter
Single ring VCO Þ low die area and low noise/spur coupling
No LO leakage issue
Need a more advanced PLL architecture (Noise attenuator) to achieve the tight DBS phase noise specifications
ADC
Medium dynamic range (6 bit)
Medium sampling frequency (100 MSPS)
Higher dynamic range (8 bit)
Higher sampling frequency (200 MSPS)
Need a good matching between I and Q stages
Dual Receiver
Dual bipolar tuner + dual demod & MPEG processor
Coupling issues between two LC-VCOs.
Easy integration of two tuners on the same die since ring-VCO’s have negligible pulling at large frequency offset.
Area
Multiple inductors for LC-VCOs Þ larger area
No inductors Þ much lower area
Integration
SiP between bipolar tuner front-end and CMOS baseband back-end
CMOS SoC with tuner-demodulator+(MPEG processor)
Cost
High packaging cost for SiP of BiCMOS tuner and CMOS demodulator.
Enables low-cost SoC of tuner+demodulator RF front end IC. This system partitioning enables the use of a single MPEG IC across cable/satellite/terrestrial product lines.
A CMOS implementation of the DBS tuner/demodulator is a cost-effective path to a single-chip DBS receiver, and a low-IF tuner is the architecture of choice towards this goal. The RF front-end requirements are relaxed by performing more signal processing in the digital domain. Such a DSP approach to solving analog CMOS non-idealities is further enabled by the ever faster digital circuitry of modern deep-submicron CMOS processes.
Adrian Maxim has received B.S.E.E., M.S.E.E. and Ph.D. degrees from the Technical University of Iasi, Romania. Dr. Maxim is now with Silicon Laboratories (Austin TX) as a Senior RF Architect working on RF tuners and wireless transceivers. His research interests are in advanced PLL synthesizer and RF front-end architectures for wireless and wireline applications. He authored three books and over 50 technical papers in IEEE Journals and Conferences.
Ramin K. Poorfard received his Ph.D. from University of Toronto in 1995. In that year he joined Bell Labs where he was involved in the GSM base-band product development for cellular phones. In 1999, he was promoted to the rank of Distinguished Member of Technical Staff. In 2000, he joined Silicon Laboratories (Austin, TX) where he worked on ADSL products and more recently on satellite receiver front ends. Dr. Poorfard’s interests are RF IC architectures and their building block integrations as well as mixed-signal design.
Bart DeCanne joined Silicon Laboraties in 2004 and currently is marketing manager in the company’s Broadcast Products group. From 1993-98 he was with Barco Broadcast & Cable, currently a division of Cisco Systems, as hardware engineer and project manager for DVB cable TV head-end products. In 1998 he joined Texas Instruments in Dallas, TX as sr. systems engineer, and from 2000-02 was strategic marketing manager for T.I.’s mixed-signal video products. Bart has a MSEE from the State University of Ghent, Belgium and an MBA from the University of Texas at Austin.
