Publication date: 26 August 2008
This article explains why the last generation of Analog-to-Digital Converter (ADC), which are based on successive approximation (SAR), did not support this signal range and why modern ADCs are moving back to this standard.
ADCs with a successive approximation register work like a weight scale [1, 2]. Fig. 1 shows that the comparator evaluates, if the input voltage Vin, which is sampled with the sample and hold capacitor (S&H), is higher or lower than a voltage, which is generated with a capacitive digital-to-analog converter (DAC or CDAC).
The DAC is approximating the input voltage with an additional bit of accuracy per clock cycle.The SAR ADC is neither the fastest converter nor the converter with the highest accuracy, but it is used most often.
The advantage of the SAR ADC compared to the high resolution delta-sigma converter is the capability of taking a snapshot of the input signal, which means that the input signal can be sampled at a very particular point in time. This is often important in industrial process control.
Further, the SAR ADC achieves higher conversion rates at a similar power dissipation. If compared to pipeline converters, the SAR ADC offers a better noise performance and consumes much lower power, which is important in battery driven systems or in systems, where the current or heat dissipation is limited by the application.
These industrial applications are often facing a rough environment, so that a high analog signal range (±10V or more) is preferred to make the signal more robust.
Unfortunately, semiconductor processes do typically not support this voltage range due to the breakdown voltages of the internal transistors. This article describes the history of SAR converter and the new high voltage approaches using special analog processes. It further gives an outlook of the next generation of products.
Until the mid nineties, ADCs normally offered a bipolar input voltage range of ±5V or ±10V. This was supported by 2mm and 3mm CMOS processes, which included very linear resistors. A typical example is the ADS7809 from Burr-Brown. Table 1 shows some of the specifications. The differential non-linearity (DNL) is achieving a true 16bit performance, but the conversion rate is low and the power consumption high.
Table 1 Specifications of a typical high voltage device of the previous generation
This is caused by the required transistor size. The comparator input for example requires a low noise differential pair. The noise of MOS transistors is a function of their transconductance gm, which itself is a function of the ration of the width W to the length L of the transistor and the current through the transistor.
The minimum length is limited by the process, the width has to be large and the current high.
The size of the devices will further cause an essential parasitic capacitance. The gate capacitance of the second gain stage inside a comparator will for example limit the speed of the first differential pair and therefore will limit the conversion rate of the converter. The converter design is therefore a trade-off between power, speed and noise.
The large transistors of this previous generation of ADCs further caused a big die size, which generated high die costs at a lower yield. The slow speed furthermore generated large test times, so that the high performance ADCs were expensive.
The large die size also required large packages like dual inline packages (DIP) or wide body surface mount packages SOIC. The research and development of ADC therefore moved away from high voltage designs and processes towards CMOS processes with lower gate length.
The first 16bit ADC (ADS8320 from Burr-Brown) on a 5V process was therefore celebrated as product of the year 1998. The noise performance was improved due to the better gm of the transistors. The power was reduced dramatically due to the lower supply voltage and the smaller parasitic capacitors. This enabled the usage of SAR ADCs in several new applications like portable and battery driven equipment such as touch screen products.
Unfortunately the reduced LSB (least significant bit) size made the converter more sensitive. Designs had to face thermal effects and packaging shifts, so that the differential linearity was limited to 14-15bits and the integral linearity to 13-14bits (also see table 2).
Table 2 Specifications of the first generation of ADCs on a 5V process
Unfortunately, a further reduction of the transistor length will not necessarily further reduce the noise. This is because the transistor noise of the comparator and the reference is not dominating anymore.
Lowering the input voltage range makes the so called kT/C noise dominant. This is a thermal noise, which is generated during sampling by the on-resistance Ron of the input switch. The noise density of a resistor nRon is described by [5].
A significant improvement in performance by lowering the gate length does not seem possible.
The key players in analog design concentrated in a novel process development, which remained the transistor length at 0.5-0.6mm and which added very particular devices for high performance analog products.
Very important are good matching resistors, which furthermore show low drift over temperature and life time. With these resistors it is possible to design high performance R-2R digital-to-analog converters (DAC8831 from TI). If in addition the voltage coefficient of the resistor is small, then string DACs are possible with very low integral non-linearity (DAC8558 from TI).
An extremely low metal pitch allows the design of complex digital interfaces and functions. Products of the previous generation typically had very simple serial or parallel inputs or outputs. New functions were added, which are controlled via an internal register map. With the help of ‘electrical fuses’ or ‘one time programmable memory’, an electrical trim was implemented, which is also controlled by the register map.
Some products even implement a variety of interfaces, which are controlled by external mode pins. Furthermore, a BiCMOS process has good bipolar transistors, which are important for amplifier and reference designs.
Such a process requires a buried n-layer, which isolates a p-well area from the substrate (see Fig. 4). As a side effect, these isolated p-well areas are used to isolate the bulk of NCH transistors from the substrate. This way, the substrate can be isolated from the noise of the digital circuitry and sensitive analog circuits can be isolated from the general substrate noise.
Most interesting are the high voltage transistors, which are implemented with a dual gate process. 36V can be applied between the drain and the source as well as the gate and the source.
The mixture of high voltage transistors and low voltage transistors can be used for interesting products such as a new generation of high-voltage ADCs.
Even though the 5V ADCs achieve a very good noise performance, they are not preferable in the industrial process control. It is not good enough to have a low noise converter, since also a robust analog front-end is required, which is used for the signal conditioning in these rough environments. ±10V input signals are automatically more robust by a factor of 4 if compared to single 5V systems. High voltage ADCs are and will therefore remain of very high interest.
A new generation of high voltage ADCs can benefit from the new process components. There are actually two approaches. One is using the resistors with the low drift and with the low voltage coefficient. It is possible to divide and level shift the ±10V input signal internally to a 0V to 5V range. The signal can then be processed with 5V transistors to remain the speed, noise and power advantages of the lower voltage transistors.
A typical example is the ADS8515 from TI. The performance however was improved with new architectures and the novel process. Table 4 compares the specifications of the previous generation (ADS7809) to the new generation (ADS8515).
This implementation has two disadvantages. First, there is a continuous current forced from the input signal. High impedance input sources will therefore generate gain errors. To keep this current low, the internal resistance needs to be high, so that the bandwidth of the ADC input is limited. This automatically requires longer sampling times and causes lower conversion rates.
Table 4 Comparison of specifications between an ADC of the previous generation (ADS7809) and the new generation (ADS8515)
In a second approach, the high voltage input signal is directly sampled on the sample capacitor through high voltage transistors. The signal is then divided by the capacitive DAC of the SAR ADC. Also this scheme has some disadvantages.
Even if the capacitors have a very good voltage coefficient, it will influence the integral linearity of the ADC. At high voltages, this is in particular true for the quadratic voltage coefficient. If a 10V signal is stored across the capacitor and if the quadratic voltage coefficient is around 1ppm/V2, then the change of the sample capacitor, is 100ppm at the endpoints, but not at the mid-scale. The integral non-linearity reaches several LSBs.
The second disadvantage is caused by the high on-resistance Ron and high parasitic capacitance Csw of the high voltage input switches. Both are non-linear related to the input voltage. They will not affect the DC performance, but AC signals are affected with distortion due to the Ron•(Csw+Cs) delay of the sample circuitry that is input voltage dependent.
Boot strapping (see Fig. 5), where the gate of the input switch is biased to the input signal plus a constant voltage and where the bulk is shorted to the input, can reduce the total harmonic distortion, but requires a severe amount of circuitry and increases the die size.
Nevertheless, sampling with high voltage switches seems to be the technique for future products. New design architectures and further process improvements will be developed to overcome the mentioned problems.
Summarized, the new high voltage products provide significant improvements in terms of speed, power and noise. Unfortunately, there are still two major limitations. The high resistance sampling switch, which further has significant parasitic capacitance, affects the total harmonic distortion (THD) at signal frequencies above 100kHz and the voltage coefficient of the capacitor generates an integral non-linearity independent on the input frequency.
It seems that further process improvements are required to solve at least the THD problem. On the other side it is time to develop a trim solution for the integral non-linearity, especially as all other DC specifications are adjustable, as are the differential non-linearity, the offset [6], the gain [7] and even the common-mode rejection.
Furthermore the high input voltage should also enable the designs to further improve the noise performance in terms of the signal-to-noise ratio. Products with 106dB are foreseeable.
[1] F. Oehme, M. Huemer and M. Pfaff, Elektronik und Schaltungstechnik, Carl Hanser Verlag, ISBN 3-446-40694-8, 2006
[2] Rudy J. van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, Springer Netherlands, ISBN 1-4020-750-6, 2003
[3] Chakravarthy Srinivasean, Kiran M. Godbole, Error correction architecture to increase speed and relax current drive requirements of SAR ADC, Patent US6747589, Texas Instruments, 2004
[4] Frank Ohnhaeuser, Mario Huemer, Reference generation for A/D converters, In the CD-ROM Proceedings of the International Symposium on Signals, Systems and Electronics (ISSSE2007), Montreal, Canada, August 2007
[5] P. Gray, R. Meyer, Analysis and Design of ANALOG INTEGRATED CIRCUITS, John Wiley & Sons, Inc., ISBN 0-471-57495-3, 1993
[6] Frank Ohnhaeuser, Miroslav Oljaca, Offset error compensation of input signals in analog-to-digital converter, Patent US6433712, Texas Instruments, 2002
[7] Robert Seymour, Method and circuit for gain and/or offset correction in a capacitor digital-to-analog converter, Patent US6922165, Texas Instruments, 2005
