Publication date: 30 January 2008
With the ability to integrate MEMS with CMOS processes, micro-electromechanical systems (MEMS) are fast becoming a mainstream electronics technology. Consequently, electronics project teams are looking for design tools to help them take advantage of this high-potential technology. Few multidisciplinary tool suites exist to support both MEMS and microelectronics design, and certainly no single software package can offer all the necessary features. Most designers today use several different pieces of software to accomplish design tasks. The inherent multidisciplinary nature of MEMS, means that both mechanical and electronic design tools have been used. The dearth of appropriate layout tools have posed a particular challenge for MEMS designers.
Deriving from the IC world, rectangles, polygons and wires are the predominant geometries. Most IC layout tools are 2D, which means that a MEMS designer has to extrapolate the three dimensionality of the fabricated device, though there are tools available to perform the 3D visualisation of the 2D masks.
Mechanical engineering tools, meanwhile, usefully incorporate curves, arcs and circles, enabling physical designers to make beams less fracture-prone, to reduce mechanical stress, and to make fluids mix and flow smoothly. Access to a fast, easy-to-use 3D or cross-section viewer is becoming more important in MEMS design. Further refinement is achieved through finite element analysis.
One of the major differences between MEMS and electronic circuit masks is the lack of design rules, and often, the absence of simple Manhattan-style geometries. (Figure 1). Furthermore, in contrast to CMOS microelectronic chips, there is a greater uncertainty between the simulated and actual performance of a new MEMS device. Fabrication and physical effects typically require intensive experimental testing and a thorough understanding before subsequent modifications are made. Only then are neglected second-order effects added back into the finite element analysis (FEA). In fact, for some devices, such as micro relays or radio frequency (RF) switches, the number of cycles to failure and failure mechanisms have only been solved through tedious experimental analyses.
Once the design is optimised, the respective process layers must be laid out, and the subsequent output then sent to high-resolution masks. Selecting the right layout tool should be regarded as a critical decision. This investment can be instrumental reducing mask and design errors, ultimately saving time and money in the manufacturing cycle. Layout tools must meet the obvious requirements: easy to use, compatible with third-party design software, and physically able to render the geometries required.
A MEMS layout tool must be able to draw any shape or form in 2D (if not 3D) space. Circles, arcs, and curves are key. Popular mechanical CAD packages offer complete control of curves, but output into GDS format can be problematic. Some electronics-oriented CAD tools, such as L-Edit MEMS from Tanner Research, offer simple arcs and toruses (circle in a circle), which can be grouped into a complex shape. With these groups, you can easily create hierarchical cells. The ability to see the hierarchy and perform global edits and revisions becomes a necessity in revisioning. An important side benefit of the hierarchical layout is memory and rendering speed. If complex curves are required (See Figure 2), then the tool must be able to program custom macros in C to create smart, scalable, and variable T-cells.
The rendering of these complex shapes can cause errors during the tape-out. One important difference in the mechanical (or DXF-based) CAD tools versus GDS-based tools is the enclosure of polygons. In masks for MEMS or semiconductor chips, the drawn shapes are either dark (chrome) or clear (etched chrome). Therefore, all drawn geometries must be closed polygons. Most semiconductor (GDS-based) CAD tools create these closed polygons.
However, in the mechanical domain, where CAD tools are used by architects and graphic designers, zero-width lines and open polygons can be drawn routinely (whether intentionally or by mistake). A mask fabricator tool cannot interpret zero-width open lines. Some error-correcting conversions enable users to merge open lines within a certain tolerance, but they are not fail-safe techniques. This factor has often been found to be the culprit behind many large problems, which sometimes require the MEMS designer to spend hours re-working the CAD drawings.
To make things worse, MEMS designs often require a challenging geometry: holes in a plate. This ‘polygon within polygon’ essentially becomes an ambiguous shape for the mask interpreter. In mechanical drawing programs, this can be handled by artificially splitting up the form into smaller repeating segments, or by splitting the holes onto a different layer and performing Boolean operations, that is, providing the CAD tools support this function. Boolean drawing and layer operations that support filled objects are the best solution, and are supported by many electronic CAD tools.
Once the designer has drawn these smooth shapes, they must be transposed or ‘pixelated’ onto the mask resolution grid in the final output. Therefore, the ability to raster curves by controlling the number of points on a fine (manufacturing) grid is key because masks are typically ‘discretised’ before output. Many mask houses still use older software and hardware with set limits on the number of points defining a polygon in GDS format. For example, if a circle with diameter of 500µm is to be fabricated in a 0.5µm mask resolution, the number of points on the perimeter of this smooth polygon will be close to 3,000. With a more complex shape, this number can easily be about 10,000. Many MEMS CAD tools have algorithms that can fracture these polygons into smaller shapes with a user-controllable number of vertices.
The scale range of MEMS designs is often four orders of magnitude (104), which requires constant zooming in and out of the design and forces the designer to be vigilant about drawing errors. A single polygon feature may be millimeters long, have µm-sized features, and need to be placed in relation to another feature with that same high precision. The accurate object snapping ability of many mechanical CAD tools has become an indispensable feature in IC drawing tools, particularly for large-scale designs. Typical snaps are to corners of polygons, circle centres, arcs and object edges, all without requiring the designer to zoom in on the exact location.
But hand-in-hand with large scale design is the potential for mask errors. As a design progresses and more layers are added, it is very easy to make mask drawing errors. These errors normally stem from either inadvertent movement of an object due to an unnoticed selection, or a screen resolution that does not allow the user to see object separation when zoomed out.
In the IC world, many of these errors can easily be caught before tape-out. How? By using strict design rule checking (DRC) engines, and by enabling better layer transparency through multiple layer rendering options. The ability to ‘see through’ the various layers is extremely useful when trying to visualise three dimensions in a two-dimensional space.
Regarding DRC, the user can customise very simple rules in today’s IC tools, such as L-Edit, that work on all objects even at the MEMS R&D level. Rules to check for minimum width and separation between layers, for polygons with more than a certain number of vertices, and for overlaps between user specified layers, can easily be established via a check box-driven system. These files can then be shared across projects to set local standards and minimise fabrication errors. With the Interactive DRC option in L-Edit, mask errors are further reduced because DRC violations are displayed and can be fixed in real-time.
In a fiercely competitive market, the next few years will bring a wave of MEMS tools that incorporate the best of IC, Mechanical CAD, and finite element modeling (FEM) in one cross-platform package. But until a true one-stop-shop MEMS suite arrives, the designer who requires both CMOS and MEMS compatibility must select from a wide range of options.
Focus on the core features that the design team needs. Be aware that selection of a capable simulation and analysis tool, might be disadvantaged by an underperforming layout engine. When it comes to integrating a CMOS design with 90% Manhattan-style geometries and 10% curves and polygons, choose the tool that gives you the capability for both. But note that some tools promise full DRC, LVS, and Spice simulation and can cost hundreds of thousands of dollars. But there are EDA tools with many of these same features and can be just as effective for the MEMS/CMOS designer, but at considerably lower cost.
Amish Desai is with Tanner Research Inc. Details of L-Edit and other Tanner design tools can be found on http://www.tanner.com or through exclusive European distributor, EDA Solutions.
